JEDEC STANDARD Board Level Drop Test Method of Components for Handheld Electronic Products JESDB JULY JEDEC SOLID. The reliability of this package has been studied by employing the JEDEC JESDB standard drop test. In this paper, the JEDEC B-condition is applied to. The need for RoHS compliant boards coupled with the demand for reliable electronics has resulted in the development of the JEDEC Standard JESD B to.
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Drop Test Simulation o Effect of Thermal Agin Ford Packaging Drop Te JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability v111 improvement of products, and assisting the purchaser in selecting b1111 obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.
JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes.
BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS
The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. No claims to be jesd2 conformance with this standard may be made unless all requirements stated in the standard are met. By downloading this kesd22 the individual agrees not to charge for or resell the resulting material.
Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement.
These handheld electronic products are more prone to being dropped during their useful service life because of their size and weight. This dropping event can not only cause mechanical failures in the jrsd22 of the device but also create electrical failures in the printed circuit board PCB assemblies mounted inside the housing due to transfer of energy through PCB supports.
The electrical failures may result from various failure modes such as cracking of circuit board, trace cracking on the board, cracking of solder interconnections between the components and the board, and the component cracks.
The primary driver of these failures is excessive flexing of circuit board due to input acceleration to the board created from dropping the handheld electronic product. This flexing of the board causes relative motion between the board and the components mounted on it, resulting in component, interconnects, or board failures. The failure is a strong function of the combination of the board design, construction, material, thickness, and surface finish; b111 material and standoff height; and component size.
The purpose is to standardize the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components while duplicating the failure modes normally observed during product level test.
The purpose of this document is to prescribe a standardized test method and reporting procedure. This is not a component qualification test and is not meant to replace any system level drop test that maybe needed to qualify a specific handheld ejsd22 product. Ejsd22 standard is not meant to cover the drop test required to simulate shipping and handling related shock of electronic components or PCB assemblies. The method is applicable to both area-array and perimeter-leaded surface mounted packages.
Correlation between test and field conditions is not yet fully established. The comparability between different test sites, data acquisition methods, and board manufacturers has not been fully demonstrated by existing data. As a result, if the data are to be used for direct comparison of component performance, matching study must first be performed to prove that the data are in fact comparable across different test sites and test conditions.
This method is not intended to substitute for full characterization testing, which might incorporate substantially larger sample sizes and increased number of drops.
Due to limited sample size and number of drops specified here, it is possible that enough failure data may not be generated in every case to perform full statistical analysis. A packaged semiconductor device. A printed circuit board assembly with components mounted on only one side of the board double-sided PCB assembly: A printed circuit board jfsd22 with components mounted on top and bottom sides of the board.
The maximum acceleration during the dynamic motion of the test apparatus. The free-fall drop height of the drop table needed to attain the prescribed peak acceleration and pulse duration. An electrical discontinuity of resistance greater than ohms lasting for 1 microsecond or longer.
A continuity test instrument capable of detecting electrical jesc22 of resistance greater than ohms lasting for 1 microsecond or longer. Since components jezd22 body sizes larger than 15 mm x 15 mm in size are not used in these applications, the maximum size of the component body covered in this standard is 15 mm x 15 mm. All components used for this testing must be daisy-chained. The daisy chain should either be done at jesc22 die level or by providing daisy chain links at the lead-frame or substrate level.
In case of non-daisy chain die, a mechanical dummy die must be used inside the package to simulate mesd22 actual structure of the package. The die size and thickness should be similar to the functional die size to be used in application. The component materials, dimensions, and assembly processes shall be representative of typical production device. The test data generated using such a board shall be correlated at least once by generating the same data on same component using the preferred board defined in this document.
This is required as typical PCB assemblies used in handheld electronic systems are constructed using high density, buildup technology.
The test board shall have a nominal thickness of 1. Table 1 provides the thickness, copper coverage, and the material for each layer. The dielectric materials shall meet the mechanical properties requirements as given in Table 2.
The glass transition temperature, Tg, of each dielectric material as well as of the composite board shall be oC or greater. The modulus and Tg of the dielectric materials shall be specified. The composite values Mesd22, and Tg shall be measured on at least one representative test board at component mounting location. The boards shall be symmetric in construction about the mid-plane of the board, except for the minor differences in the top and bottom two layers.
Since a typical product board may have a combination of microvia in pad and no vias in pad for area array packages for routing purposes, it is required that such components BGAs, CSPs, etc be tested on board with both microvia and non-microvia PCB pads. This shall be accomplished by designing double sided boards with mirror component footprint on each side top and bottom of the board.
For board Side A, the microvias in pads shall be created with laser ablation with jeesd22 diameter of microns. The vias shall then be plated resulting in straight or near straight walls.
The capture pad diameter shall be at least microns. In that case, the components shall be mounted on each side of the board. The board shall still be designed as double-sided with footprint of similar sized components on each side.
Although daisy-chain nets will typically not require plated though holes PTH other than those required for manual probe pads and connectors, the test board shall contain PTH in the component region 1. There shall be 20 plated through holes per square centimeter in the component region. The through holes shall have the drill diameter of microns and finished plated hole diameter of microns. The PTH pad diameters shall be microns for the outer layer and microns for the inner layers.
It is recommended that the component mounting pads on the PCB be designed as per the specification in Table 3 for area array devices. All component attachment pads shall be non-solder-mask-defined NSMD with solder mask clearance of 75 microns between the edge of the pad and the edge of solder mask.
Smaller clearance can be used as long as it does not cause any solder mask encroachment on pads due to misregistration. This includes all traces making contact with solder joint interconnect as well as all internal layers. A trace width of microns shall be used for all traces outside of component region.
The board shall have matching daisy chain pattern such that one or multiple nets are formed through all interconnects after component mounting. Wherever necessary, additional jed22 points within each net shall be incorporated for failure location identification. Each additional test point shall be clearly labeled using row column format of the package. All jedd22 and traces within and just outside the component footprint shall be done on jeed22 2 and layer 8 for area array packages and layer 1 and layer 8 for perimeter leaded packages.
Component length and width.
BOARD LEVEL DROP TEST METHOD OF COMPONENTS FOR HANDHELD ELECTRONIC PRODUCTS | JEDEC
The overall board size shall be mm X 77 mm that can accommodate up to 15 components of same type in a 3 row by 5 column format. The maximum component size shall be 15 mm in length or width and there shall be at least 5 and 8 mm gap between the components in x- and y-direction, respectively. All 15 sites on each side of the board top and bottom shall have the same component footprint. For example, a 9 x 9 pad array can be designed to accommodate suitably designed daisy chain components with 8 x 8, 7 x 7, 8 x 9, or any other ball array combination.
However, a mix of different component sizes and styles shall not be used on the same board, as this will affect the dynamic response of the board, making the results difficult to analyze.
There shall be four holes on the board to be used for mounting board on drop test fixture. The locations of these holes are shown in Figure 1. All components must be located within the 95 mm X 61 mm box shown by the dashed line in Figure 1 defined by the outer edges of all outer components. The x, y location of the center of each component location is listed in Table 4, using the center of lower left screw hole as datum.
The area of the board in the length direction outside of components shall be restricted for labeling, through holes, edge fingers, and any other fixtures, if needed. Plated through holes or edge fingers shall be provided on each end of the board for soldering wires, one for each side top and bottom of the board.
Board thickness, warpage, and pad sizes shall also be measured using a sampling plan. A visual inspection shall be performed on all boards for solder mask registration, contamination, and daisy chain connection. It is recommended that boards should be inspected and accepted as per IPC-A, Class 3 acceptability criteria.
One board shall also be used to measure the mechanical properties modulus, and Tg of the board at the component location using DMA and TMA method.
The mechanical property measurements are not required for every board lot, unless the fab process, material, or vendor is changed from lot to lot. The test boards shall be assembled using best known methods of printed circuit assembly process, representative of production methods. At least one board shall be used to adjust board mounting process such as paste printing, placement, and reflow profile. All assemblies shall be single side only unless the component is anticipated for use in mirror-sided board assemblies.
Electrical continuity test shall also be performed on all mounted units to detect any opens or shorts. Since the drop performance is a function of component location on the board, testing with components mounted on all 15 locations will provide useful information to the users of this data OEMs in proper layout of their product board.
Because of various design for test and design for failure analysis practices used in the industry, it is recognized that populating boards with all 15 locations may not leave enough room between components for large number of test points to properly identify the exact failure location. Therefore, options are provided for mounting just 1 or 5 components on the board using the following locations: Location U8 5-component configurations: The additional data shall directly compare the effect of optional component mounting 1 or 5 components to the preferred component mounting configuration.
Depending on the number of components mounted per board, Table 5 shall be used to determine the minimum quantity of assembled board required for testing and total number of components to be tested. Sample sizes greater than specified below can be used to generate statistically sufficient data.
In case of rectangular components, the longer side of the component should be parallel to the longer side of the board when mounted. This test method is not meant to address the drop test methods required to simulate shipping and handling related shock of electronic subassemblies. Means shall be provided in the apparatus such as automatic braking mechanism to eliminate bounce and to prevent multiple shocks to the board. Figure 3 shows the typical drop test apparatus where the drop table travels down on guide rods and strikes the rigid fixture.